The present invention relates to a semiconductor integrated circuit, and in particular, to an apparatus and method of generating a power up signal of a semiconductor memory.
Typically, the power up signal is enabled according to whether a level of power supplied to a semiconductor integrated circuit is stabilized to a predetermined level or more.
When an initial operation, in which power starts to be supplied, is performed, the power up signal is kept in a disable state (for example, in a low level) and internal information of the memory is initialized, that is, reset.
Then, if the power up signal is enabled (for example, in a high level), an active operation is prepared after a predetermined time passes (for example, 100 us) such that the semiconductor memory can normally operate.
Further, a fast power up phenomenon occurs when a power up sequence is rapidly executed, during which the semiconductor integrated circuit enters a deep power down mode in which power is rapidly cut off according to an external command and then rapidly returns to a normal mode, or when the level of power rapidly changes due to noise.
As shown in FIG. 1, a conventional power up signal generating apparatus includes resistors R1 and R2, an inverter IV1, and first, second and third transistors M1, M2, M3.
The resistors R1 and R2 are connected between a power terminal VDDI and a ground terminal. The first transistor M1 has a source connected to the power terminal VDDI and a gate connected to the ground terminal. The second transistor M2 has a drain connected to a drain of the first transistor M1, a source connected to the ground terminal, and a gate connected to a connection node A of the resistors R1 and R2. The inverter IV1 has an input terminal connected to a connection node B of the first transistor M1 and the second transistor M2, to output a power up signal PWRUP. The third transistor M3 has a drain connected to the power terminal VDDI and a gate and a source connected to the connection node A of the resistors R1 and R2.
In the conventional power up signal generating apparatus, a current flows into the node B through the first transistor M1 such that the inverter IV1 disables the power up signal PWRUP in a low level, until the level of the node A becomes equal to or more than a threshold voltage of the second transistor M2.
When the level of the node A becomes equal to or more than the threshold voltage of the second transistor M2, the current supplied through the first transistor M1 is discharged to the ground terminal through the second transistor M2 such that the level of the node B becomes a low level. Then, the inverter IV1 enables the power up signal PWRUP in a high level.
The level of the power up signal PWRUP is determined according to the amount of a current that flows through the first transistor M1 and the amount of a current that is discharged to the ground terminal through the second transistor M2.
As shown in FIG. 2, in the conventional power up signal generating apparatus, even though a predetermined period of the power up signal PWRUP is disabled in a low level at the beginning of the operation, if the level of the node A rises equal to or more than a predetermined level, the power up signal PWRUP is enabled in a high level.
As a period C of FIG. 2, when the fast power up phenomenon occurs, in which power rapidly drops and then rises at a lus slope, in a case where a temperature at that time is high (HOT, for example, 90° C.), enough current is supplied by the first transistor M1 of FIG. 1. Thus, the level of the node B in the period C of FIG. 2 rises to a level at which a logical value is determined as ‘high’. Therefore, the power up signal PWRUP is disabled in a low level and then enabled in a high level after a predetermined time.
However, in a case where a temperature at that time is low (COLD, for example, 40° C.), since enough current is not supplied by the first transistor M1 of FIG. 1, the level of the node B in the period C of FIG. 2 cannot rise to the level at which the logical value is determined as ‘high’. Therefore, the power up signal PWRUP is not disabled in the low level and thus a power up fail phenomenon when the power up signal PWRUP keeps a high level occurs.
As described above, the conventional power up signal generating apparatus has a problem in that, when the fast power up phenomenon occurs in a state where the operation temperature is low, an error occurs in generating the power up signal. The initial operation for memory information cannot be performed, which makes it difficult to perform the normal operation of the semiconductor memory.